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? freescale semiconductor, inc., 2004. all rights reserved. this document contains information on a new produc t. specifications and information herein are subject to change without notice. freescale semiconductor advance information mc9328mxl/d rev. 5, 08/2004 mc9328mxl package information plastic package (mapbga?225 or 256) ordering information see table 2 on page 5 mc9328mxl 1 introduction the i.mx family builds on the dragonball family of application processors which ha ve demonstrated leadership in the portable handheld market . continuing this legacy, the i.mx (media extensions) se ries provides a leap in performance with an arm9? microprocessor core and highly integrated system functions. the i.mx products specifically address the requi rements of the personal, portable product market by pr oviding intelligent integrated peripherals, an advanced processor core, and power management capabilities. the new mc9328mxl features the advanced and power- efficient arm920t? core that operates at speeds up to 200 mhz. integrated module s, which include an lcd controller, usb support, and an mmc/sd host controller, support a suite of peripherals to enhance any product seeking to provide a rich multimedia ex perience. it is packaged in either a 256-pin mold array process-ball grid array (mapbga) or 225-pin pbga package. figure 1 shows the functional block diagram of the mc9328mxl. contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 2 signals and connections . . . . . . . . . . . . . . . . . . . .6 3 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4 pin-out and package information. . . . . . . . . . . . .79 contact information . . . . . . . . . . . . . . . . . last page
mc9328mxl advance information, rev. 5 2 freescale semiconductor introduction figure 1. mc9328mxl functional block diagram 1.1 conventions this document uses the following conventions: ? overbar is used to indicate a signal that is active when pulled low: for example, reset . ? logic level one is a voltage that corresponds to boolean true (1) state. ? logic level zero is a voltage that corresponds to boolean false (0) state. ?to set a bit or bits means to establish logic level one. ?to clear a bit or bits means to establish logic level zero. ?a signal is an electronic construct whose state conv eys or changes in stat e convey information. ?a pin is an external physical connec tion. the same pin can be used to connect a number of signals. ? asserted means that a discrete signal is in active logic state. ? active low signals change from logic le vel one to logic level zero. ? active high signals change from logic le vel zero to logic level one. ? negated means that an asserted discret e signal changes logic state. ? active low signals change from logic le vel zero to logic level one. ? active high signals change from logic le vel one to logic level zero. ? lsb means least significant bit or bits , and msb means most significant bit or bits . references to low and high bytes or words are spelled out. ? numbers preceded by a percent sign (%) are bi nary. numbers preceded by a dollar sign ($) or 0x are hexadecimal. watchdog gpio lcd controller jtag/ice cgm timer 1 & 2 pwm standard bootstrap connectivity system control i 2 c mmc/sd spi 1 and uart 1 uart 2 usb device memory stick? human interface video port multimedia multimedia power rtc bus dmac interrupt vmmu cpu complex mc9328mxl i cache aipi 1 aipi 2 d cache eim & arm9tdmi? system i/o control (pllx2) controller control (11 chnl) sdramc accelerator spi 2 host controller ssi/i 2 s
introduction mc9328mxl advance information, rev. 5 freescale semiconductor 3 1.2 features to support a wide variety of applications, the mc9328mxl offers a robust array of features, including the following: ? arm920t? microprocessor core ? ahb to ip bus interfaces (aipis) ? external interface module (eim) ? sdram controller (sdramc) ? dpll clock and powe r control module ? two universal asynchronous receiv er/transmitters (uart 1 and uart 2) ? two serial peripheral interfaces (spi1 and spi2) ? two general-purpose 32-bit counters/timers ? watchdog timer ? real-time clock/sampling timer (rtc) ? lcd controller (lcdc) ? pulse-width modulation (pwm) module ? universal serial bus (usb) device ? multimedia card and secure digita l (mmc/sd) host controller module ? memory stick? host controller (mshc) ? direct memory access controller (dmac) ? synchronous serial interfa ce and inter-ic sound (ssi/i 2 s) module ? inter-ic (i 2 c) bus module ?video port ? general-purpose i/o (gpio) ports ? bootstrap mode ? multimedia accelerator (mma) ? power management features ? operating voltage range: 1.7 v to 1.98 v core, 1.7 v to 3.3v i/o ? 256-pin mapbga package ? 225-pin mapbga package 1.3 target applications the mc9328mxl is targeted for adva nced information appliances, smart phones, web browsers, digital mp3 audio players, handheld computer s, and messaging applications.
mc9328mxl advance information, rev. 5 4 freescale semiconductor introduction 1.4 revision history table 1 provides revision history for th is release. this history includes tec hnical content revisions only and not stylistic or grammatical changes. 1.5 product documentation the following documents are required for a complete description of the mc 9328mxl and are necessary to design properly with the device. especially for those not familiar with the arm9 20t processor or previous dragonball products, the following documents are helpful when used in co njunction with this document. arm architecture reference manual (arm ltd., order number arm ddi 0100) arm9dt1 data sheet manual (arm ltd., order number arm ddi 0029) arm technical reference manual (arm ltd., order number arm ddi 0151c) emt9 technical reference manual (arm ltd., order number ddi o157e) mc9328mxl product brief (order number mc9328mxlp/d) mc9328mxl reference manual (order number mc9328mxlrm/d) the motorola manuals are available on th e motorola semiconductors web site at http://www.motorola.com/sem iconductors. these documents may be downl oaded directly from the motorola web site, or printed versions may be ordered. the arm ltd. documentation is available from http://www.arm.com. table 1. mc9328mxl data sheet revision history rev. 5 revision location revision throughout clarified instances where bclk signal is burst clock. section 3.3, ?power sequence requirements? on page 12 added reference to an2537.
introduction mc9328mxl advance information, rev. 5 freescale semiconductor 5 1.6 ordering information table 2 provides ordering informatio n for both the 256-lead mold array process ball grid array (mapbga) package and the 225-lead bga package. table 2. mc9328mxl ordering information package type frequency temperatu re solderball type order number 256-lead mapbga 150 mhz -40 o c to 85 o c standard mc9328mxlcvh15(r2) pb-free mc9328mxlcvm15(r2) 200 mhz 0 o c to 70 o c standard mc9328mxlvh20(r2) pb-free mc9328mxlvm20(r2) -30 o c to 70 o c standard mc9328mxldvh20(r2) pb-free MC9328MXLDVM20(r2) 225-lead mapbga 150 mhz -40 o c to 85 o c standard mc9328mxlcvf15(r2) pb-free mc9328mxlcvp15(r2) 200 mhz 0 o c to 70 o c standard mc9328mxlvf20(r2) pb-free mc9328mxlvp20(r2) -30 o c to 70 o c standard mc9328mxldvf20(r2) pb-free mc9328mxldvp20(r2)
mc9328mxl advance information, rev. 5 6 freescale semiconductor signals and connections 2 signals and connections table 3 identifies and describes the mc9328mxl signals that are assigned to package pins. the signals are grouped by the internal module that they are connected to. table 3. mc9328mxl signal descriptions signal name function/notes external bus/chip-select (eim) a[24:0] address bus signals d[31:0] data bus signals eb0 msb byte strobe?active low external enable byte signal that controls d [31:24]. eb1 byte strobe?active low external enable byte signal that controls d [23:16]. eb2 byte strobe?active low external enable byte signal that controls d [15:8]. eb3 lsb byte strobe?active low external enable byte signal that controls d [7:0]. oe memory output enable?active low output enables external data bus. cs [5:0] chip-select?the chip-select signals cs [3:2] are multiplexed with csd [1:0] and are selected by the function multiplexing control register (fmcr). by default csd [1:0] is selected. ecb active low input signal sent by a flash device to the eim whenever the flas h device must terminate an on-going burst sequence and initiate a new (long first access) burst sequence. lba active low signal sent by a flash device causing t he external burst device to latch the starting burst address. bclk (burst clock) clock signal sent to external synchronous memori es (such as burst flash) during burst mode. rw rw signal?indicates whether extern al access is a read (high) or write (low) cycle. used as a we input signal by external dram. dtack dtack signal?the external input data acknowledge signal. when using the external dtack signal as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not terminated by the external dtack signal after 1022 clock counts have elapsed. bootstrap boot [3:0] system boot mode select?the operational system boot mode of the mc9328mxl upon system reset is determined by the settings of these pins. sdram controller sdba [4:0] sdram/syncflash non-interleave mode bank address multiplexed with address signals a [15:11]. these signals are logically equivalent to core address p_addr [25:21] in sdram/syncflash cycles. sdiba [3:0] sdram/syncflash interleave addressing mode bank address multiplexed with address signals a [19:16]. these signals are logically equivalent to core address p_addr [12:9] in sdram/syncflash cycles. ma [11:10] sdram address signals ma [9:0] sdram address signals which are multiplexed with ad dress signals a [10:1]. ma [9:0] are selected on sdram/syncflash cycles. dqm [3:0] sdram data enable csd0 sdram/syncflash chip-select signal which is multiplexed with the cs2 signal. these two signals are selectable by programming the system control register.
signals and connections mc9328mxl advance information, rev. 5 freescale semiconductor 7 csd1 sdram/syncflash chip-select signa l which is multiplexed with cs3 signal. these two signals are selectable by programming the system control register. by default, csd1 is selected, so it can be used as syncflash boot chip-select by pro perly configuring boot [3:0] input pins. ras sdram/syncflash row address select signal cas sdram/syncflash column address select signal sdwe sdram/syncflash write enable signal sdcke0 sdram/syncflash clock enable 0 sdcke1 sdram/syncflash clock enable 1 sdclk sdram/syncflash clock reset_sf syncflash reset clocks and resets extal16m crystal input (4 mhz to 16 mhz), or a 16 mhz oscillat or input when the internal oscillator circuit is shut down. xtal16m crystal output extal32k 32 khz crystal input xtal32k 32 khz crystal output clko clock out signal selected from internal clock signals. reset_in master reset?external active low schmitt trigger input signal. when this signal goes active, all modules (except the reset module and the clock control module) are reset. reset_out reset out?internal active low output signal from the watchdog timer module and is asserted from the following sources: power-on reset, external reset (reset_in ), and watchdog time-out. por power on reset?internal active high schmitt tri gger input signal. the por signal is normally generated by an external rc circuit designed to detect a power-up event. jtag trst test reset pin?external active low signal used to asynchronously initialize the jtag controller. tdo serial output for test instructions and data. changes on the falling edge of tck. tdi serial input for test instructions and data. sampled on the rising edge of tck. tck test clock to synchronize test logic and control register access through the jtag port. tms test mode select to sequence the jtag test cont roller?s state machine. sampled on the rising edge of tck. dma big_endian big endian?input signal that determines the configurat ion of the external chip-select space. if it is driven logic-high at reset, the external chip-select sp ace will be configured to little endian. if it is driven logic-low at reset, the external chip -select space will be configured to big endian. dma_req external dma request pin. etm etmtracesync etm sync signal which is multiplexed with a24. etmtracesync is selected in etm mode. table 3. mc9328mxl signal descriptions (continued) signal name function/notes
mc9328mxl advance information, rev. 5 8 freescale semiconductor signals and connections etmtraceclk etm clock signal which is multiplexed with a23. etmtraceclk is selected in etm mode. etmpipestat [2:0] etm status signals which are mu ltiplexed with a [22:20]. etmpipestat [2 :0] are selected in etm mode. etmtracepkt [7:0] etm packet signals which are multiplexed with ecb , lba , bclk(burst clock), pa17, a [19:16]. etmtracepkt [7:0] are selected in etm mode. cmos sensor interface csi_d [7:0] sensor port data csi_mclk sensor port master clock csi_vsync sensor port vertical sync csi_hsync sensor port horizontal sync csi_pixclk sensor port data latch clock lcd controller ld [15:0] lcd data bus?all lcd signals are driven low after reset and when lcd is off. flm/vsync frame sync or vsync?this signal also serves as the clock signal output for the gate driver (dedicated signal sps for sharp panel hr-tft). lp/hsync line pulse or h sync lsclk shift clock acd/oe alternate crystal di rection/output enable. contrast this signal is used to control the lcd bias voltage as contrast control. spl_spr program horizontal scan direction (sharp panel dedicated signal). ps control signal output for source driver (sharp panel dedicated signal). cls start signal output for gate driver . this signal is an inverted version of ps (sharp panel dedicated signal). rev signal for common electrode driving signal pr eparation (sharp panel dedicated signal). spi 1 and 2 spi1_mosi master out/slave in spi1_miso slave in/master out spi1_ss slave select (selectable polarity) spi1_sclk serial clock spi1_spi_rdy serial data ready spi2_txd spi2 master txdata output?this si gnal is multiplexed with a gpi/o pin yet shows up as a primary or alternative signal in the signal multiplex schem e table. please refer to the spi and gpio chapters in the mc9328mxl reference manual for informatio n about how to bring this signal to the assigned pin. spi2_rxd spi2 master rxdata input?this signal is multiplex ed with a gpi/o pin yet shows up as a primary or alternative signal in the signal multiplex scheme ta ble. please refer to the spi and gpio chapters in the mc9328mxl reference manual for information about how to bring this signal to the assigned pin. table 3. mc9328mxl signal descriptions (continued) signal name function/notes
signals and connections mc9328mxl advance information, rev. 5 freescale semiconductor 9 spi2_ss spi2 slave select?this signal is multiplexed with a gpi/o pin yet shows up as a primary or alternative signal in the signal multiplex scheme ta ble. please refer to the spi and gpio chapters in the mc9328mxl reference manual for information about how to bring this signal to the assigned pin. spi2_sclk spi2 serial clock?this si gnal is multiplexed wi th a gpi/o pin yet show s up as a primary or alternative signal in the signal multiplex scheme ta ble. please refer to the spi and gpio chapters in the mc9328mxl reference manual for information about how to bring this signal to the assigned pin. general purpose timers tin timer input capture or timer input clock?the signal on this input is ap plied to both timers simultaneously. tmr2out timer 2 output usb device usbd_vmo usb minus output usbd_vpo usb plus output usbd_vm usb minus input usbd_vp usb plus input usbd_suspnd usb suspend output usbd_rcv usb receive data usbd_oe usb oe usbd_afe usb analog front end enable secure digital interface sd_cmd sd command?if the system designer does not wish to make use of the internal pull-up, via the pull- up enable register, a 4.7k?69k external pull up resistor must be added. sd_clk mmc output clock sd_dat [3:0] data?if the system designer does not wish to make use of the internal pull-up, via the pull-up enable register, a 50k?69k external pull up resistor must be added. memory stick interface ms_bs memory stick bus state (output)?serial bus control signal ms_sdio memory stick serial data (input/output) ms_sclko memory stick serial clock (input)?serial protocol clock source for sclk divider ms_sclki memory stick external clo ck (output)?test clock input pin for sclk divider. this pin is only for test purposes, not for use in application mode. ms_pi0 general purpose input0?can be used for me mory stick insertion/extraction detect ms_pi1 general purpose input1?can be used for me mory stick insertion/extraction detect uarts ? irda/auto-bauding uart1_rxd receive data uart1_txd transmit data table 3. mc9328mxl signal descriptions (continued) signal name function/notes
mc9328mxl advance information, rev. 5 10 freescale semiconductor signals and connections uart1_rts request to send uart1_cts clear to send uart2_rxd receive data uart2_txd transmit data uart2_rts request to send uart2_cts clear to send uart2_dsr data set ready uart2_ri ring indicator uart2_dcd data carrier detect uart2_dtr data terminal ready serial audio port ? ssi (configurable to i 2 s protocol) ssi_txdat transmit data ssi_rxdat receive data ssi_txclk transmit serial clock ssi_rxclk receive serial clock ssi_txfs transmit frame sync ssi_rxfs receive frame sync i 2 c i2c_scl i 2 c clock i2c_sda i 2 c data pwm pwmo pwm output digital supply pins nvdd digital supply for the i/o pins nvss digital ground for the i/o pins supply pins ? analog modules avdd supply for analog blocks avss quiet ground for analog blocks internal power supply qvdd power supply pins for silicon internal circuitry qvss ground pins for silicon internal circuitry table 3. mc9328mxl signal descriptions (continued) signal name function/notes
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 11 3 specifications this section contains the electrical specifications and timing diagrams for the mc9328mxl processor. 3.1 maximum ratings table 4 provides information on maximum ratings. substrate supply pins svdd supply routed through substrate of package; not to be bonded sgnd ground routed through substrate of package; not to be bonded table 4. maximum ratings rating symbol minimum maximum unit supply voltage v dd -0.3 3.3 v maximum operating temperature range mc9328mxlvh20/mc9328mxlvm20/ mc9328mxlvf20/mc9328mxlvp20 t a 070c maximum operating temperature range mc9328mxldvh20/MC9328MXLDVM20/ mc9328mxldvf20/mc9328mxldvp20 t a -30 70 c maximum operating temperature range mc9328mxlcvh15/mc9328mxlcvm15/ mc9328mxlcvf15/mc9328mxlcvp15 t a -40 85 c esd at human body model (hbm) vesd_hbm ? 2000 v esd at machine model (mm) vesd_mm ? 100 v latch-up current ilatchup ? 200 ma storage temperature test -55 150 c power consumption pmax 800 1 1. a typical application with 30 pads simultaneously switchi ng assumes the gpio toggling and instruction fetches from the arm core-that is, 7x gpio, 15x data bus, and 8x address bus. 1300 2 2. a worst-case application with 70 pads simultaneously swit ching assumes the gpio toggling and instruction fetches from the arm core-that is, 32x gpio, 30x data bus, 8x address bus. these calculations are based on the core running its heaviest os application at 200mhz, and wh ere the whole image is running out of sdram. qvdd at 2.0v, nvdd and avdd at 3.3v, therefor e, 180ma is the worst measurement recorded in the factory environment, max 5ma is consumed for osc pads, with each toggle gpio consuming 4ma. mw table 3. mc9328mxl signal descriptions (continued) signal name function/notes
mc9328mxl advance information, rev. 5 12 freescale semiconductor specifications 3.2 recommended operating range table 5 provides the recommended oper ating ranges for the supply voltag es. the mc9328mxl has multiple pairs of vdd and vss power supply and return pins. qvdd and qv ss pins are used for internal logic. all other vdd and vss pins are for the i/o pads voltage supply, and each pair of vdd and vss provid es power to the enclosed i/ o pads. this design allows different peripheral supply voltage levels in a system. because avdd pins are supply voltages to the analog pads, it is recommended to isolate and noise-filter the avdd pins from other vdd pins. for more information about i/o pads groupi ng per vdd, please refer to table 3 on page 6. 3.3 power sequence requirements for required power-up and power-down sequencing, please refer to the "power-up sequen ce" section of application note an2537 on th e i.mx website page. 3.4 dc electrical characteristics table 6 contains both maximum and minimum dc characteristics of the mc9328mxl. table 5. recommended operating range rating symbol minimum maximum unit i/o supply voltage (if using mshc, spi, bta, usbd, lcd and csi which are only 3 v interfaces) nvdd 2.70 3.30 v i/o supply voltage (if not using the pe ripherals listed above) nvdd 1.70 3.30 v internal supply voltage (core = 150 mhz) qvdd 1.70 1.90 v internal supply voltage (core = 200 mhz) qvdd 1.80 2.00 v analog supply voltage avdd 1.70 3.30 v table 6. maximum and minimum dc characteristics number or symbol parameter min typical max unit iop full running operating current at 1.8v for qvdd, 3.3v for nvdd/avdd (core = 96 mhz, system = 96 mhz, mpeg4 decoding playback from external memory card to both external ssi audio decoder and tft display panel, and os with mmu enabled memory system is running on external sdram). ? qvdd at 1.8v = 120ma; nvdd+avdd at 3.0v = 30ma ?ma sidd 1 standby current (core = 150 mhz, qvdd = 1.8v, temp = 25 c) ?25 ? a sidd 2 standby current (core = 150 mhz, qvdd = 1.8v, temp = 55 c) ?45 ? a sidd 3 standby current (core = 150 mhz, qvdd = 2.0v, temp = 25 c) ?35 ? a
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 13 3.5 ac electrical characteristics the ac characteristics consist of output delays, input setup and hold times, and signal skew times. all signals are specified relative to an appropriate edge of other sign als. all timing specifications are specified at a system operating frequency from 0 mhz to 96 mhz (core operating frequency 150 mhz) with an operating supply voltage from v dd min to v dd max under an operating temperature from t l to t h . all timing is measured at 30 pf loading. sidd 4 standby current (core = 150 mhz, qvdd = 2.0v, temp = 55 c) ?60 ? a v ih input high voltage 0.7v dd ?vdd+0.2v v il input low voltage ? ? 0.4 v v oh output high voltage (i oh = 2.0 ma) 0.7v dd ?vddv v ol output low voltage (i ol = -2.5 ma) ? ? 0.4 v i il input low leakage current (v in = gnd, no pull-up or pull-down) ??1 a i ih input high leakage current (v in =v dd , no pull-up or pull-down) ??1 a i oh output high current (v oh =0.8v dd , v dd =1.8v) ??4.0ma i ol output low current (v ol =0.4v, v dd =1.8v) -4.0 ? ? ma i oz output leakage current (v out =v dd , output is tri-stated) ??5 a c i input capacitance ? ? 5 pf c o output capacitance? ? ? 5 pf table 7. tristate signal timing pin parameter minimum maximum unit tristate time from tristate activate until i/o becomes hi-z ? 20.8 ns table 8. 32k/16m oscillator signal timing parameter minimum rms maximum unit extal32k input jitter (peak to peak) ? 5 20 ns table 6. maximum and minimum dc characteristics (continued) number or symbol parameter min typical max unit
mc9328mxl advance information, rev. 5 14 freescale semiconductor specifications 3.6 embedded trace macrocell all registers in the etm9 are prog rammed through a jtag interface. the interface is an extension of the arm920t processor?s tap controller, and is assigned scan chain 6. th e scan chain consists of a 40-bit shift register comprised of the following: ? 32-bit data field ? 7-bit address field ? a read/write bit the data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address field, and a 1 into the read/write bit. a register is read by scanning its address into the a ddress field and a 0 into the read/write bit. the 32-bit data field is ignored. a read or a write takes place when the tap controller enters the update-dr state. the timing diagram for the etm9 is shown in figure 2. see table 9 for the etm9 timing parameters used in figure 2. figure 2. trace port timing diagram extal32k startup time 800 ? ? ms extal16m input jitter (peak to peak) ? tbd tbd ? extal16m startup time tbd ? ? ? table 9. trace port timi ng diagram parameter table ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum 1 clk frequency 0 85 0 100 mhz 2a clock high time 1.3 ? 2 ? ns 2b clock low time 3 ? 2 ? ns table 8. 32k/16m oscillator signal timing (continued) parameter minimum rms maximum unit traceclk 4b 4a 3b 2a 1 output trace port 3a valid data valid data 2b traceclk (half-rate clocking mode)
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 15 3a clock rise time ? 4 ? 3 ns 3b clock fall time ? 3 ? 3 ns 4a output hold time 2.28 ? 2 ? ns 4b output setup time 3.42 ? 3 ? ns table 9. trace port timing diagram parameter table (continued) ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum
mc9328mxl advance information, rev. 5 16 freescale semiconductor specifications 3.7 dpll timing specifications parameters of the dpll are given in table 10. in this table, t ref is a reference clock period after the pre-divider and t dck is the output double clock period. table 10. dpll specifications parameter test conditions minimum typical maximum unit reference clock freq range vcc = 1.8v 5 ? 100 mhz pre-divider output clock freq range vcc = 1.8v 5 ? 30 mhz double clock freq range vcc = 1.8v 80 ? 220 mhz pre-divider factor (pd) ? 1 ? 16 ? total multiplication factor (mf) includes both integer and fractional parts 5?15? mf integer part ? 5 ? 15 ? mf numerator should be less than the denominator 0 ? 1022 ? mf denominator ? 1 ? 1023 ? pre-multiplier lock-in time ? ? ? 312.5 sec freq lock-in time after full reset fol mode for non-integer mf (does not include pre-multi lock-in time) 250 280 (56 s) 300 t ref freq lock-in time after partial reset fol mode for non-integer mf (does not include pre-multi lock-in time) 220 250 (50 s) 270 t ref phase lock-in time after full reset fpl mode and integer mf (does not include pre-multi lock-in time) 300 350 (70 s) 400 t ref phase lock-in time after partial reset fpl mode and integer mf (does not include pre-multi lock-in time) 270 320 (64 s) 370 t ref freq jitter (p-p) ? ? 0.005 (0.01%) 0.01 2t dck phase jitter (p-p) integer mf, fpl mode, vcc=1.8v ? 1.0 (10%) 1.5 ns power supply voltage ? 1.7 ? 2.5 v power dissipation fol mode, integer mf, f dck = 200 mhz, vcc = 1.8v ?? 4mw
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 17 3.8 reset module the timing relationships of the re set module with the por and rese t_in are shown in figure 3 and figure 4. note: be aware that nvdd must ramp up to at least 1.8v before qvdd is powered up to prevent forward biasing. figure 3. timing relationship with por por reset_por reset_dram hreset reset_out clk32 hclk 90% avdd 10% avdd 1 2 3 4 exact 300ms 7 cycles @ clk32 14 cycles @ clk32
mc9328mxl advance information, rev. 5 18 freescale semiconductor specifications figure 4. timing relationship with reset_in table 11. reset module timing parameter table ref no. parameter 1.8v 0.10v 3.0v 0.30v unit min max min max 1 width of input power_on_reset note 1 1. por width is dependent on the 32 or 32.768 khz crys tal oscillator start-up time. design margin should allow for crystal tolerance, i.mx chip variations , temperature impact, and supply voltage influence. through the process of supplying crystals for use wi th cmos oscillators, crystal manufacturers have developed a working knowledge of start-up time of th eir crystals. typically, start-up times range from 400 ms to 1.2 seconds for this type of crystal. if an external stable clock source (already running) is used instead of a crystal , the width of por should be ignored in calculating timi ng for the start-up process. ? note 1 ?? 2 width of internal power_on_reset (clk32 at 32 khz) 300 300 300 300 ms 3 7k to 32k-cycle stretcher for sdram reset 7 7 7 7 cycles of clk32 4 14k to 32k-cycle stretcher for internal system reset hresert and output reset at pin reset_out 14 14 14 14 cycles of clk32 5 width of external hard-reset reset_in 4 ? 4 ? cycles of clk32 6 4k to 32k-cycle qualifier 4 4 4 4 cycles of clk32 14 cycles @ clk32 reset_in clk32 hclk 5 4 hreset reset_out 6
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 19 3.9 external interface module the external interface module (e im) handles the interface to devi ces external to the mc9328mxl, including the generation of chip-sel ects for external peripherals and memory. the timing diagram for the eim is shown in figure 5, and table 12 on page 20 defines the parameters of signals. figure 5. eim bus timing diagram 1a 1b 2a 2b 3b 3a 4a 4b 4c 4d 5a 5b 5c 5d 6a 6a 6b 6c 7a 7b 7c 8a 8b 9b 9c 9a 9a 7d (hclk) bus clock address chip-select read (write ) oe (rising edge) lba (negated rising edge) oe (falling edge) burst clock (rising edge) lba (negated falling edge) eb (falling edge) eb (rising edge) burst clock (falling edge) read data write data (negated falling) write data (negated rising) dtack 10a 10a
mc9328mxl advance information, rev. 5 20 freescale semiconductor specifications table 12. eim bus timing parameter table ref no. parameter 1.8v 0.10v 3.0v 0.30v unit min typical max min typical max 1a clock fall to address valid 2.48 3.31 9.11 2.4 3.2 8.8 ns 1b clock fall to address invalid 1.55 2.48 5.69 1.5 2.4 5.5 ns 2a clock fall to chip-select valid 2.69 3.31 7.87 2.6 3.2 7.6 ns 2b clock fall to chip-select invalid 1.55 2.48 6.31 1.5 2.4 6.1 ns 3a clock fall to read (write ) valid 1.35 2.79 6.52 1.3 2.7 6.3 ns 3b clock fall to read (write ) invalid 1.86 2.59 6.11 1.8 2.5 5.9 ns 4a clock 1 rise to output enable valid 1. clock refers to the system clock signal , hclk, generated from the system pll 2.32 2.62 6.85 2.3 2.6 6.8 ns 4b clock 1 rise to output enable invalid 2.11 2.52 6.55 2.1 2.5 6.5 ns 4c clock 1 fall to output enable valid 2.38 2.69 7.04 2.3 2.6 6.8 ns 4d clock 1 fall to output enable invalid 2.17 2.59 6.73 2.1 2.5 6.5 ns 5a clock 1 rise to enable bytes valid 1.91 2.52 5.54 1.9 2.5 5.5 ns 5b clock 1 rise to enable bytes invalid 1.81 2.42 5.24 1.8 2.4 5.2 ns 5c clock 1 fall to enable bytes va lid 1.97 2.59 5.69 1.9 2.5 5.5 ns 5d clock 1 fall to enable bytes in valid 1.76 2.48 5.38 1.7 2.4 5.2 ns 6a clock 1 fall to load burst address valid 2.07 2.79 6.73 2.0 2.7 6.5 ns 6b clock 1 fall to load burst address invalid 1.97 2.79 6.83 1.9 2.7 6.6 ns 6c clock 1 rise to load burst address invalid 1.91 2.62 6.45 1.9 2.6 6.4 ns 7a clock 1 rise to burst clock rise 1.61 2.62 5.64 1.6 2.6 5.6 ns 7b clock 1 rise to burst clock fall 1.61 2.62 5.84 1.6 2.6 5.8 ns 7c clock 1 fall to burst clock rise 1.55 2.48 5.59 1.5 2.4 5.4 ns 7d clock 1 fall to burst clock fall 1.55 2.59 5.80 1.5 2.5 5.6 ns 8a read data setup time 5.54 ? ? 5.5 ? ? ns 8b read data hold time 0 ? ? 0 ? ? ns 9a clock 1 rise to write data valid 1.81 2.72 6.85 1.8 2.7 6.8 ns 9b clock 1 fall to write data inva lid 1.45 2.48 5.69 1.4 2.4 5.5 ns 9c clock 1 rise to write data invalid 1.63 ? ? 1.62 ? ? ns 10a dtack setup time 2.52 ? ? 2.5 ? ? ns
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 21 3.9.1 dtack signal description the dtack signal is the external inpu t data acknowledge signal. when using the external dtack signal as a data acknowledge signal, the bus time-out moni tor generates a bus error when a bus cycle is not terminated by the external dtack signal after 1022 hclk counts have elapsed. only cs5 group is designed to support dtack signal function when using the external dtack signal for data acknowledgement. 3.9.2 dtack signal timing figure 6 shows the access cycle timing used by chip-sel ect 5. the signal values and units of measure for this figure are found in table 13. figure 6. dtack timing , wsc=111111, dtack_sel=0 table 13. access cycle timing parameters ref no. characteristic 1.8v 0.10v 3.0v 0.30v unit min max min max 1cs5 asserted to oe asserted ?t?tns 2 external dtack input setup from cs5 asserted 0?0?ns 3cs5 pulse width 3t ? 3t ? ns 4 external dtack input hold after cs5 is negated 0 1.5t 0 1.5t ns 5oe negated after cs5 is negated 0 4.5 0 4 ns note: 1. n is the number of wait st ates in the current memory ac cess cycle. the max n is 1022. 2. t is the system clock period (system clock is 96 mhz). 3. the external dtack input requirement is eliminated when cs5 is programmed to use internal wait state. cs5 rw oe ext_dtack hclk int_dtack 1 2 3 4 5
mc9328mxl advance information, rev. 5 22 freescale semiconductor specifications figure 7. dtack timing , wsc=111111, dtack_sel=1 table 14. access cycle timing parameters ref no. characteristic 1.8v 0.10v 3.0v 0.30v unit min max min max 1 external dtack input setup from cs5 asserted 0?0?ns note: 1. n is the number of wait states in the current memory access cycle. the max n is 1022. 2. t is the system clock period (system clock is 96 mhz). 3. the external dtack input requirement is eliminated when cs5 is programmed to use internal wait state. cs5 rw oe ext_dtack (wait ) hclk int_dtack 1
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 23 3.9.3 eim external bus timing the timing diagrams in this se ction show the timing of accesses to memory or a peripheral. figure 8. wsc = 1, a.half/e.half hclk hsel_weim_cs[0] htrans hwrite haddr hready weim_hrdata weim_hready weim_bclk weim_addr weim_cs weim_r/w weim_lba weim_oe weim_eb (ebc=0) weim_eb (ebc=1) weim_data_in read seq/nonseq v1 last valid data last valid address read v1 v1 v1
mc9328mxl advance information, rev. 5 24 freescale semiconductor specifications figure 9. wsc = 1, wea = 1, wen = 1, a.half/e.half hclk hsel_weim_cs[0] htrans hwrite haddr hready hwdata weim_hready weim_bclk weim_addr weim_cs [0] weim_r/w weim_lba weim_oe weim_eb weim_data_out write nonseq v1 last valid data last valid address weim_hrdata write data (v1) unknown last valid data v1 write last valid data write data (v1)
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 25 figure 10. wsc = 1, oea = 1, a.word/e.half hclk hsel_weim_cs[0] htrans hwrite haddr hready weim_hready weim_bclk weim_addr weim_cs [0] weim_r/w weim_lba weim_oe weim_eb (ebc=1) weim_data_in weim_hrdata weim_eb (ebc=0) read nonseq v1 last valid data address v1 v1 word read address v1 + 2 last valid addr 1/2 half word 2/2 half word
mc9328mxl advance information, rev. 5 26 freescale semiconductor specifications figure 11. wsc = 1, wea = 1, wen = 2, a.word/e.half hclk hsel_weim_cs[0] htrans hwrite haddr hready weim_hready weim_bclk weim_addr weim_cs [0] weim_r/w weim_lba weim_oe weim_eb weim_data_out weim_hrdata hwdata write nonseq v1 last valid data address v1 write data (v1 word) write address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 27 figure 12. wsc = 3, oea = 2, a.word/e.half hclk hsel_weim_cs[3] htrans hwrite haddr hready weim_hready weim_bclk weim_addr weim_cs [3] weim_r/w weim_lba weim_oe weim_eb (ebc=0) weim_data_in weim_hrdata weim_eb (ebc=1) read nonseq v1 last valid data address v1 v1 word address v1 + 2 last valid addr 1/2 half word 2/2 half word read
mc9328mxl advance information, rev. 5 28 freescale semiconductor specifications figure 13. wsc = 3, wea = 1, wen = 3, a.word/e.half hclk hsel_weim_cs[3] htrans hwrite haddr hready weim_hready weim_bclk weim_addr weim_cs [3] weim_r/w weim_lba weim_oe weim_data_out] weim_hrdata weim_eb hwdata write nonseq v1 last valid data address v1 write data (v1 word) address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data write last valid data
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 29 figure 14. wsc = 3, oea = 4, a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready weim_bclk weim_addr weim_cs [2] weim_r/w weim_lba weim_oe weim_data_in weim_hrdata weim_eb (ebc=0) weim_eb (ebc=1) read nonseq v1 address v1 v1 word address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data read
mc9328mxl advance information, rev. 5 30 freescale semiconductor specifications figure 15. wsc = 3, wea = 2, wen = 3, a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready weim_bclk weim_addr weim_cs [2] weim_r/w weim_lba weim_oe weim_data_out hwdata weim_eb weim_hrdata write nonseq v1 last valid data address v1 write data (v1 word) address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data write last valid data
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 31 figure 16. wsc = 3, oen = 2, a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready weim_bclk weim_addr weim_cs [2] weim_r/w weim_lba weim_oe weim_data_in weim_hrdata weim_eb (ebc=0) weim_eb (ebc=1) read nonseq v1 address v1 v1 word address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data read
mc9328mxl advance information, rev. 5 32 freescale semiconductor specifications figure 17. wsc = 3, oea = 2, oen = 2, a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready weim_bclk weim_addr weim_cs [2] weim_r/w weim_lba weim_oe weim_data_in weim_hrdata weim_eb (ebc=0) weim_eb (ebc=1) read nonseq v1 address v1 v1 word address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data read
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 33 figure 18. wsc = 2, wws = 1, wea = 1, wen = 2, a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready weim_bclk weim_addr weim_cs [2] weim_r/w weim_lba weim_oe weim_hrdata weim_eb weim_data_out hwdata write nonseq v1 address v1 unknown address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data last valid data write data (v1 word) last valid data write
mc9328mxl advance information, rev. 5 34 freescale semiconductor specifications figure 19. wsc = 1, wws = 2, wea = 1, wen = 2, a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready weim_bclk weim_addr weim_cs [2] weim_r/w weim_lba weim_oe weim_hrdata weim_eb weim_data_out hwdata write nonseq v1 address v1 unknown address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data last valid data write data (v1 word) write last valid data
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 35 figure 20. wsc = 2, wws = 2, wea = 1, wen = 2, a.half/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready weim_bclk weim_addr weim_cs [2] weim_r/w weim_lba weim_oe weim_data_out weim_hrdata weim_eb (ebc=0) weim_eb (ebc=1) read nonseq v1 address v1 write data address v8 last valid addr last valid data read write nonseq v8 last valid data read data write read data last valid data write data hwdata weim_data_in
mc9328mxl advance information, rev. 5 36 freescale semiconductor specifications figure 21. wsc = 2, wws = 1, wea = 1, wen = 2, edc = 1, a.half/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready weim_bclk weim_addr weim_cs [2] weim_r/w weim_lba weim_oe weim_data_in weim_hrdata weim_eb (ebc=0) weim_eb (ebc=1) read nonseq v1 address v1 address v8 last valid addr read data last valid data read write nonseq v8 weim_data_out hwdata last valid data write data read data write last valid data write data read write idle
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 37 figure 22. wsc = 2, csa = 1, wws = 1, a.word/e.half write nonseq v1 address v1 address v1 + 2 last valid addr last valid data write data (word) write last valid data last valid data write data (1/2 half word) write data (2/2 half word) hclk hsel_weim_cs[4] htrans hwrite haddr hready weim_hready weim_bclk weim_addr weim_cs weim_r/w weim_lba weim_oe weim_hrdata weim_eb weim_data_out hwdata
mc9328mxl advance information, rev. 5 38 freescale semiconductor specifications figure 23. wsc = 3, csa = 1, a.half/e.half hclk hsel_weim_cs[4] htrans hwrite haddr hready weim_hready weim_bclk weim_addr weim_cs [4] weim_r/w weim_lba weim_oe weim_data_in weim_hrdata weim_eb (ebc=0) weim_eb (ebc=1) read nonseq v1 address v1 address v8 last valid addr last valid data read last valid data read data write data write nonseq v8 write read data write data last valid data weim_data_out hwdata
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 39 figure 24. wsc = 2, oea = 2, cnc = 3, bcm = 0, a.half/e.half hclk hsel_weim_cs[4] htrans hwrite haddr hready weim_hready weim_bclk weim_addr weim_cs [4] weim_r/w weim_lba weim_oe weim_data_in weim_hrdata weim_eb (ebc=0) weim_eb (ebc=1) read nonseq v1 address v1 read data (v1) address v2 last valid last valid data read read seq v2 idle read data (v2) cnc read data (v1) read data (v2)
mc9328mxl advance information, rev. 5 40 freescale semiconductor specifications figure 25. wsc = 2, oea = 2, wea = 1, wen = 2, cnc = 3, a.half/e.half hclk hsel_weim_cs[4] htrans hwrite haddr hready weim_hready weim_bclk weim_addr weim_cs [4] weim_r/w weim_lba weim_oe weim_data_in weim_hrdata weim_eb (ebc=0) weim_eb (ebc=1) read nonseq v1 address v1 address v8 last valid addr read data last valid data read weim_data_out hwdata write nonseq v8 idle last valid data write data read data write cnc last valid data write data
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 41 figure 26. wsc = 3, sync = 1, a.half/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready weim_bclk weim_addr] weim_cs [2] weim_r/w weim_lba weim_oe weim_data_in weim_hrdata weim_eb (ebc=0) weim_eb (ebc=1) nonseq nonse read read idle v1 v5 address v1 last valid addr address v5 read v1 word v2 word v5 word v6 word weim_ecb
mc9328mxl advance information, rev. 5 42 freescale semiconductor specifications figure 27. wsc = 2, sync = 1, dol = [1/0], a.word/e.word hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready weim_bclk weim_addr weim_cs [2] weim_r/w weim_lba weim_oe weim_data_in weim_hrdata weim_eb (ebc=0) weim_eb (ebc=1) weim_ecb nonseq seq read idle v1 seq seq read read read v2 v3 v4 last valid data v1 word v2 word v3 word v4 word address v1 last valid addr read v1 word v2 word v3 word v4 word
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 43 figure 28. wsc = 2, sync = 1, dol = [1/0], a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready weim_bclk weim_addr weim_cs [2] weim_r/w weim_lba weim_oe weim_data_in weim_hrdata weim_eb (ebc=0) weim_eb (ebc=1) weim_ecb address v1 last valid read v1 1/2 v1 2/2 v2 1/2 v2 2/2 address v2 nonseq seq read idle v1 read v2 last valid data v1 word v2 word
mc9328mxl advance information, rev. 5 44 freescale semiconductor specifications figure 29. wsc = 7, oea = 8, sync = 1, dol = 1, bcd = 1, bcs = 2, a.word/e.half non seq seq read idle v1 read v2 last valid data v1 word v2 word address v1 last read v1 1/2 v1 2/2 v2 1/2 v2 2/2 hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready weim_bclk weim_addr weim_cs [2] weim_r/w weim_lba weim_oe weim_data_in weim_hrdata weim_eb (ebc=0) weim_eb (ebc=1) weim_ecb
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 45 figure 30. wsc = 7, oea = 8, sync = 1, dol = 1, bcd = 1, bcs = 1, a.word/e.half hclk hsel_weim_cs[2] htrans hwrite haddr hready weim_hready weim_bclk weim_addr weim_cs [2] weim_r/w weim_lba weim_oe weim_data_in weim_hrdata weim_eb (ebc=0) weim_eb (ebc=1) weim_ecb non seq seq read idle v1 read v2 last valid data v1 word v2 word address v1 last read v1 1/2 v1 2/2 v2 1/2 v2 2/2
mc9328mxl advance information, rev. 5 46 freescale semiconductor specifications 3.10 spi timing diagrams to utilize the internal transmit (tx) and receive (rx) data fifos when the spi 1 module is configured as a master, two control signals are used for data transfer rate control: the ss signal (output) and the spi_rdy signal (input). the spi 1 sample period control register (periodreg1) and the spi 2 sample period control register (periodreg2) can also be programmed to a fixed data transfer rate for either spi 1 or spi 2. when the sp i 1 module is configured as a slav e, the user can configure the spi 1 control register (controlreg1) to match the external spi master?s ti ming. in this configuration, ss becomes an input signal, and is used to latch data into or load data out to the internal data shift registers, as well as to increment the data fifo. figure 31 through figure 35 show the timing relationship of the master spi using different tr iggering mechanisms. figure 31. master spi timing diagram using spi_rdy edge trigger figure 32. master spi timing diagram using spi_rdy level trigger figure 33. master spi timing diagram ignore spi_rdy level trigger figure 34. slave spi timing diag ram fifo advanced by bit count 1 2 3 5 4 ss spirdy sclk, mosi, miso ss spirdy sclk, mosi, miso sclk, mosi, miso ss (output) ss (input) sclk, mosi, miso
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 47 figure 35. slave spi timing diagram fifo advanced by ss rising edge 3.11 lcd controller this section includes tim ing diagrams for the lcd controller. fo r detailed timing diagrams of the lcd controller with various display configurations , refer to the lcd controller chapter of the mc9328mxl reference manual . figure 36. sclk to ld timing diagram table 15. timing parameter table for figure 31 through figure 35 ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum m inimum maximum 1 spi_rdy to ss output low 2t 1 1. t = cspi system clo ck period (perclk2). ? 2t 1 ?ns 2ss output low to first sclk edge 3 tsclk 2 2. tsclk = period of sclk. ? 3 tsclk 2 ?ns 3 last sclk edge to ss output high 2 tsclk ? 2 tsclk ? ns 4ss output high to spi_rdy low 0?0?ns 5ss output pulse width tsclk + wait 3 3. wait = number of bit clocks (s clk) or 32.768 khz clocks per sa mple period co ntrol register. ? tsclk + wait 3 ?ns 6ss input low to first sclk edge t?t?ns 7ss input pulse width t ? t ? ns 6 7 ss (input) sclk, mosi, miso 1 lsclk ld[15:0]
mc9328mxl advance information, rev. 5 48 freescale semiconductor specifications figure 37. 4/8/16 bit/pixe l tft color mode panel timing table 16. lcdc sclk timing parameter table ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum 1 sclk to ld valid ? 2 ? 2 ns table 17. 4/8/16 bit/pixe l tft color mode panel timing symbol description minimum corresponding register value unit t1 end of oe to b eginning of vsyn t5+t6 +t7+t9 (vwait1t2)+t5+t6+t7+t9 ts t2 hsyn period xmax+5 xma x+t5+t6+t7+t9+t10 ts t3 vsyn pulse widt h t2 vwidth(t2) ts t4 end of vsyn to beginning of oe 2 vwait2(t2) ts t5 hsyn pulse width 1 hwidth+1 ts t6 end of hsyn to beginning to t9 1 hwait2+1 ts line 1 line y t1 t4 t3 (1,1) (1,2) (1,x) t5 t7 t6 xmax vsyn hsyn oe ld[15:0] sclk hsyn oe ld[15:0] t2 t8 vsyn t9 t10 display region non-display region line y
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 49 t7 end of oe to beginning of hsyn 1 hwait1+1 ts t8 sclk to valid ld data -3 3 ns t9 end of hsyn idle2 to vsyn edge (for non-display region) 22ts t9 end of hsyn idle2 to vsyn edge (for display region) 11ts t10 vsyn to oe active (sharp = 0) when vwait2 = 0 11ts t10 vsyn to oe active (sharp = 1) when vwait2 = 0 22ts note: ts is the sclk period which equals lcdc_clk / (pcd + 1). normally lcdc_clk = 15ns. vsyn, hsyn and oe can be programmed as active high or active low. in figure 37, all 3 signals are active low. the polarity of sclk and ld[15:0] can also be programmed. sclk can be programmed to be deactivated during the vsyn pulse or the oe deasserted period. in figure 37, sclk is always active. for t9 non-display region, vsyn is non-active. it is used as an reference. xmax is defined in pixels. table 17. 4/8/16 bit/pixel tft co lor mode panel timing (continued) symbol description minimum corresponding register value unit
mc9328mxl advance information, rev. 5 50 freescale semiconductor specifications 3.12 multimedia card/secure digital host controller the dma interface block controls all data routing be tween the external data bus (dma access), internal mmc/sd module data bus, and internal system fifo access through a dedicated state machine that monitors the status of fifo content (empty or fu ll), fifo address, and byte/block counters for the mmc/sd module (inner system) and the application (user programming). figure 38. chip-select read cycle timing diagram table 18. sdhc bus timing parameter table ref no. parameter 1.8v 0.10v 3.0 0.30v unit minimum maximum minimum maximum 1 clk frequency at data transfer mode (pp) 1 ?10/30 cards 1. c l 100 pf / 250 pf (10/30 cards) 0 25/5 0 25/5 mhz 2 clk frequency at identification mode 2 2. c l 250 pf (21 cards) 0 400 0 400 khz 3a clock high time 1 ?10/30 cards 6/33 ? 10/50 ? ns 3b clock low time 1 ?10/30 cards 15/75 ? 10/50 ? ns 4a clock fall time 1 ?10/30 cards ? 10/50 (5.00) 3 ? 10/50 ns 4b clock rise time 1 ?10/30 cards ? 14/67 (6.67) 3 ? 10/50 ns 5a input hold time 3 ?10/30 cards 3. c l 25 pf (1 card) 5.7/5.7 ? 5/5 ? ns 5b input setup time 3 ?10/30 cards 5.7/5.7 ? 5/5 ? ns 6a output hold time 3 ?10/30 cards 5.7/5.7 ? 5/5 ? ns 6b output setup time 3 ?10/30 cards 5.7/5.7 ? 5/5 ? ns 7 output delay time 3 0 16 0 14 ns bus clock 5b 6b 6a 7 5a 4a 3a 1 cmd_dat input cmd_dat output 4b 3b valid data valid data valid data valid data 2
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 51 3.12.1 command respon se timing on mmc/sd bus the card identification and card op eration conditions timing are processe d in open-drain mode. the card response to the host comm and starts after exactly n id clock cycles. for the card address assignment, set_rca is also processed in th e open-drain mode. the minimum dela y between the host command and card response is ncr clock cycles as illustrated in fi gure 39. the symbols for fi gure 39 through figure 43 are defined in table 19. figure 39. timing diagra ms at identification mode after a card receives its rca, it switches to data transfer mode. as shown on the first diagram in figure 40, sd_cmd lines in this mo de are driven with push-pull driv ers. the command is followed by a period of two z bits (allowing time for direction switching on the bus) and then by p bits pushed up by the responding card. the other two diagrams show the separating periods n rc and n cc . table 19. state signal parameters for figure 39 through figure 43 card active host active symbol definition symbol definition z high impedance state s start bit (0) d data bits t transmitter bit (host = 1, card = 0) * repetition p one-cycle pull-up (1) crc cyclic redundancy check bits (7 bits) e end bit (1) set_rca timing identification timing host command cid/ocr n id cycles cmd content s t e z z s t content z z ****** crc z host command cid/ocr n cr cycles cmd content s t e z z s t content z z ****** crc z
mc9328mxl advance information, rev. 5 52 freescale semiconductor specifications figure 40. timing diagrams at data transfer mode figure 41 on page 53 shows basic read operation timing. in a read operation, the sequence starts with a single block read command (which specifies the start ad dress in the argument field). the response is sent on the sd_cmd lines as usual. data transmission from the card starts after the access time delay n ac , beginning from the last bit of the read command. if the sy stem is in multiple block read mode, the card sends a continuous flow of data blocks with distance n ac until the card sees a stop transmission command. the data stops two clock cycles after the end bit of the stop command. timing of command sequences (all modes) timing response end to next cmd start (data transfer mode) command response timing (data transfer mode) host command response n cr cycles cmd content s t e z z p p s t content crc e z z ****** crc z response host command n rc cycles cmd content s t e z z s t content crc e z z ****** crc z host command host command n cc cycles cmd content s t e z z s t content crc e z z ****** crc z
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 53 figure 41. timing diagrams at data read figure 42 shows the basic write operation timing. as w ith the read operation, after the card response, the data transfer starts after n wr cycles. the data is suffixed with crc check bits to allo w the card to check for transmission errors. the card send s back the crc check result as a cc st atus token on th e data line. if there was a transmission error, the card sends a ne gative crc status (101); ot herwise, a positive crc status (010) is returned. th e card expects a continuous flow of data blocks if it is configured to multiple block mode, with the flow terminated by a stop transmission command. n ac cycles read data timing of single block read n ac cycles read data timing of multiple block read n ac cycles n st timing of stop command (cmd12, data transfer mode) host command response n cr cycles cmd content s t e z z p p s t content crc e z ****** crc dat z****z z z p p s d ***** d d d dat z****z z z p p s d ***** ****** d d d p ***** p s d d d d ****** host command response n cr cycles cmd content s t e z z p p s t content crc e z ****** crc ***** read data host command response n cr cycles cmd content s t e z z p p s t content crc e z ****** crc valid read data dat ***** z z e ***** d d d d d d d d z
mc9328mxl advance information, rev. 5 54 freescale semiconductor specifications figure 42. timing diagrams at data write write data busy write data write data host command response n cr cycles cmd dat timing of the block write command n wr cycles busy crc status cmd dat timing of the multiple block write command content crc status n wr cycles crc status e z z p p p p ****** z z p p s crc e z z s e z p p s content crc e z z s e s e z x x x x x x l*l x x x x x x status status dat content z z p p s crc e z z x x z p p s content crc e z z x x x x x x x x x x z n wr cycles x x x x x x z****z z z z p p s content crc e z z s e s e z l*l status x x x x x x x z x x x e z z p p s content crc z z z dat z****z content s t crc e z z p p s t content crc e z z p ****** ****** p p p
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 55 the stop transmission command may occur when the ca rd is in different states. figure 43 shows the different scenarios on the bus. figure 43. stop transmission during different scenarios write data stop transmission during data transfer from the host. busy (card is programming) stop transmission during crc status transfer from the card. stop transmission received after last data block. card becomes busy programming. stop transmission received after last data block. card becomes busy programming. host command card response n cr cycles cmd content s t e z z p p s t content crc e z z ****** host command content s t crc e dat ****** d d d d d d z z z z d d d d d d d e z z s l z z z z z z z z z z z z z z z z z z z z z z e dat ****** d d d d d d z z z z d z z s z z s l z z z z z z z z z z z z z z z z z z z z z z e crc e crc dat ****** s l z z z z z z z z z z z z z z z z z z z z z z z z z z e dat ****** z z z z z z z z z z z z z z z z z z z z s l z z z z z z z z z z z z z z z z z z z z z z e z
mc9328mxl advance information, rev. 5 56 freescale semiconductor specifications 3.12.2 sdio-irq and re adwait service handling in sdio, there is a 1-bit or 4-bit interrupt respon se from the sdio peripheral card. in 1-bit mode, the interrupt response is simply that th e sd_dat[1] line is held low. the sd _dat[1] line is not used as data in this mode. the memory controller generates an interrupt according to this low and the system interrupt continues until the source is removed (s d_dat[1] returns to its high level). in 4-bit mode, the interrupt is less simple. the interrupt triggers at a pa rticular period called the "interrupt period" during the data access, and the controller must sample sd_dat[1] during this short period to determine the irq status of the attached card. the in terrupt period only happens at the boundary of each block (512 bytes). table 20. timing values for figure 39 through figure 43 parameter symbol minimum maximum unit parameter mmc/sd bus clock, clk (all values are referred to minimum (vih) and maximum (vil) mmc/sd bus clock, clk (all values are referred to minimum (vih) and maximum (vil) command response cycle ncr 2 64 clock cycles command response cycle identification respon se cycle nid 5 5 clock cycles identification response cycle access time delay cycle nac 2 taac + nsac clock cycles access time delay cycle command read cycle nrc 8 ? clock cycles command read cycle command-command cycle ncc 8 ? clock cycles command-command cycle command write cycle nwr 2 ? clock cycles command write cycle stop transmission cycle nst 2 2 clock cycles stop transmission cycle taac: data read access time -1 defined in csd register bit[119:112] nsac: data read access time -2 in clk cycles (nsac100) defined in csd register bit[111:104] taac: data read access time -1 defined in csd register bit[119:112] nsac: data read access time -2 in clk cycles (nsac100) defined in csd register bit[111:104]
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 57 figure 44. sdio irq timing diagram readwait is another feature in sdio that allows the us er to submit commands during the data transfer. in this mode, the block temporarily pauses the data transf er operation counter and related status, yet keeps the clock running, and allows the user to submit commands as normal. afte r all commands are submitted, the user can switch back to the data transfer operation and all counter and status values are resumed as access continues. figure 45. sdio readwait timing diagram 3.13 memory stick host controller the memory stick protocol requires three interface signal line connec tions for data transfers: ms_bs, ms_sdio, and ms_sclko. communication is always initiated by the mshc and operates the bus in either four-state or two-state access mode. the ms_bs signal classifies data on the sdio into one of four states (bs0, bs1, bs2, or bs3) according to its attribute and transfer direction. bs0 is the in t transfer state, and duri ng this state no packet transmissions occur. during the bs1, bs2, and bs3 states, packet comm unications are executed. the bs1, bs2, and bs3 states are regarded as one packet le ngth and one communicatio n transfer is always completed within one packet length (in fo ur-state access mode). the memory stick usually operates in four state acces s mode and in bs1, bs2, and bs3 bus states. when an error occurs during packet communication, the mode is shifted to two-state access mode, and the bs0 and bs1 bus states are automatically repeat ed to avoid a bus collision on the sdio. interrupt period irq irq dat[1] for 4-bit l h interrupt period dat[1] for 1-bit cmd content s t e z z p e z z ****** z z response crc s z z e s block data e s block data dat[1] for 4-bit dat[2] for 4-bit cmd ****** p s t e z z ****** cmd52 z crc e z z s block data l l l l l l l l l l l l l l l l l l l l l h z s e s block data e block data z z l h e s block data
mc9328mxl advance information, rev. 5 58 freescale semiconductor specifications figure 46. mshc si gnal timing diagram table 21. mshc signal timing parameter table ref no. parameter 3.0 0.3v unit minimum maximum 1 ms_sclki frequency ? 25 mhz 2 ms_sclki high pulse width 20 ? ns 3 ms_sclki low pulse width 20 ? ns 4 ms_sclki rise time ? 3 ns 5 ms_sclki fall time ? 3 ns 6 ms_sclko frequency 1 ?25mhz 7 ms_sclko high pulse width 1 20 ? ns 8 ms_sclko low pulse width 1 15 ? ns 9 ms_sclko rise time 1 ?5ns 10 ms_sclko fall time 1 ?5ns ms_sclko 11 ms_bs ms_sdio(output) ms_sdio (input) ms_sdio (input) 11 12 12 13 14 15 16 (red bit = 0) (red bit = 1) ms_sclki 1 6 2 3 7 8 4 5 9 10
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 59 11 ms_bs delay time 1 ?3ns 12 ms_sdio output delay time 1,2 ?3ns 13 ms_sdio input setup time for ms_sclko rising edge (red bit = 0) 3 18 ? ns 14 ms_sdio input hold time for ms_sclko rising edge (red bit = 0) 3 0?ns 15 ms_sdio input setup time for ms_sclko falling edge (red bit = 1) 4 23 ? ns 16 ms_sdio input hold time for ms_sclko falling edge (red bit = 1) 4 0?ns 1. loading capacitor condition is less than or equal to 30pf. 2. an external resistor (100 ~ 200 ohm) should be inse rted in series to provide current control on the ms_sdio pin, because of a possib ility of signal conflict between the ms_sdio pin and memory stick sdio pin when the pin direction changes. 3. if the msc2[red] bit = 0, mshc samples ms _sdio input data at ms_sclko rising edge. 4. if the msc2[red] bit = 1, mshc samples ms_sdio input data at ms_sclko falling edge. table 21. mshc signal timing parameter table (continued) ref no. parameter 3.0 0.3v unit minimum maximum
mc9328mxl advance information, rev. 5 60 freescale semiconductor specifications 3.14 pulse-width modulator the pwm can be programmed to select one of two cl ock signals as its source frequency. the selected clock signal is passed through a divider and a prescaler before being input to th e counter. the output is available at the pulse-width modulator output (pwm o) external pin. its timing diagram is shown in figure 47 and the parameters are listed in table 22. figure 47. pwm output timing diagram 3.15 sdram controller a write to an address within the memory region in itiates the program sequence. the first command issued to the syncflash is load comman d register. the value in a [7:0 ] determines which operation the command performs. for this write setup operation, an address of 0x40 is hardware generated. the bank and other address lines are driven with the address to be programmed. the next command is active which registers the row address and confirms the bank addr ess. the third command supplies the column address, re-confirms the bank address, and suppl ies the data to be written. syncflash does not support burst writes, therefore a burst terminate command is not required. a read to the memory region initiates the status read sequence. the first comman d issued to the syncflash is the load command register with a [7:0] set to 0x70 which correspon ds to the read status register operation. the bank and other address lines are driv en to the selected address . the second command is table 22. pwm output timing parameter table ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum 1 system clk frequency 1 1. c l of pwmo = 30 pf 0870100mhz 2a clock high time 1 3.3 ? 5/10 ? ns 2b clock low time 1 7.5 ? 5/10 ? ns 3a clock fall time 1 ?5?5/10ns 3b clock rise time 1 ?6.67?5/10ns 4a output delay time 1 5.7 ? 5 ? ns 4b output setup time 1 5.7 ? 5 ? ns system clock 2a 1 pwm output 3b 2b 3a 4b 4a
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 61 active which sets up the status register read. the ba nk and row addresses are driven during this command. the third command of the triplet is read. bank and column addresses ar e driven on the address bus during this command. data is re turned from memory on the low order 8 data bits following the cas latency. figure 48. sdram/syncflas h read cycle timing diagram table 23. sdram ti ming parameter table ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum 1 sdram clock high-level width 2.67 ? 4 ? ns 2 sdram clock low-level width 6?4?ns 3 sdram clock cycle time 11.4 ? 10 ? ns 3s cs, ras, cas, we, dqm setup time 3.42 ? 3 ? ns sdclk cs cas we ras addr dq dqm row/ba col/ba 3s 3h 3s 3h 3s 3 s 3h 3h 3h 4s 4h 5 3s 3 2 1 8 data 7 6 note: cke is high during the read/write cycle.
mc9328mxl advance information, rev. 5 62 freescale semiconductor specifications 3h cs, ras, cas, we, dqm hold time 2.28 ? 2 ? ns 4s address setup time 3.42 ? 3 ? ns 4h address hold time 2.28 ? 2 ? ns 5 sdram access time (cl = 3) ? 6.84 ? 6 ns 5 sdram access time (cl = 2) ? 6.84 ? 6 ns 5 sdram access time (cl = 1) ? 22 ? 22 ns 6 data out hold time 2.85 ? 2.5 ? ns 7 data out high-impedance time (cl = 3) ? 6.84 ? 6 ns 7 data out high-impedance time (cl = 2) ? 6.84 ? 6 ns 7 data out high-impedance time (cl = 1) ? 22 ? 22 ns 8 active to read/write command period (rc = 1) t rcd 1 ? t rcd 1 ?ns 1. t rcd = sdram clock cycle time. this settings can be found in the mc9328m xl reference manual. table 23. sdram timing parameter table (continued) ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 63 figure 49. sdram/syncflash write cycle timing diagram table 24. sdram write timing parameter table ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum 1 sdram clock high-level width 2.67 ? 4 ? ns 2 sdram clock low-level width 6?4?ns 3 sdram clock cycle time 11.4 ? 10 ? ns 4 address setup time 3.42 ? 3 ? ns 5 address hold time 2.28 ? 2 ? ns 6 precharge cycle period 1 t rp 2 ? t rp 2 ?ns 7 active to read/write command delay t rcd 2 ? t rcd 2 ?ns sdclk cs cas we ras addr dq dqm / ba row/ba 3 4 6 1 col/ba data 2 5 7 8 9
mc9328mxl advance information, rev. 5 64 freescale semiconductor specifications figure 50. sdram refresh timing diagram 8 data setup time 4.0 ? 2 ? ns 9 data hold time 2.28 ? 2 ? ns 1. precharge cycle timing is incl uded in the write timing diagram. 2. t rp and t rcd = sdram clock cycle time. these settings can be found in the mc9328mxl reference manual. table 25. sdram refresh timing parameter table ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum 1 sdram clock high-level width 2.67 ? 4 ? ns 2 sdram clock low-level width 6?4?ns table 24. sdram write timing parameter table (continued) ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum sdclk cs cas we ras addr dq dqm ba 3 4 6 1 2 5 7 row/ba 7
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 65 figure 51. sdram self-refresh cycle timing diagram 3 sdram clock cycle time 11.4 ? 10 ? ns 4 address setup time 3.42 ? 3 ? ns 5 address hold time 2.28 ? 2 ? ns 6 precharge cycle period t rp 1 ? t rp 1 ?ns 7 auto precharge command period t rc 1 ? t rc 1 ?ns 1. t rp and t rc = sdram clock cycle time. these settings c an be found in the mc9328mxl reference manual. table 25. sdram refresh timi ng parameter table (continued) ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum sdclk cs cas ras addr dq dqm ba we cke
mc9328mxl advance information, rev. 5 66 freescale semiconductor specifications 3.16 usb device port four types of data transfer modes exist for the usb mo dule: control transfers, bulk transfers, isochronous transfers, and interrupt transfers. from the perspectiv e of the usb module, the interrupt transfer type is identical to the bulk data transfer mode, and no additional ha rdware is supplied to su pport it. this section covers the transfer modes and ho w they work from the ground up. data moves across the usb in packets. groups of p ackets are combined to form data transfers. the same packet transfer mechanism applies to bulk, interrupt, an d control transfers. isochronous data is also moved in the form of packets, however, because isochronous pipes are given a fixed portion of the usb bandwidth at all times, there is no end-of-transfer. figure 52. usb device timing diagram for data transfer to usb transceiver (tx) table 26. usb device timing parameter table for data transfer to usb transceiver (tx) ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum 1t roe_vpo ; usbd_roe active to usbd_vpo low 83.14 83.47 83.14 83.47 ns 2t roe_vmo ; usbd_roe active to usbd_vmo high 81.55 81.98 81.55 81.98 ns 3t vpo_roe ; usbd_vpo high to usbd_roe deactivated 83.54 83.80 83.54 83.80 ns usbd_afe (output) usbd_roe (output) usbd_vpo (output) usbd_vmo (output) usbd_suspnd (output) usbd_rcv (input) usbd_vp (input) usbd_vm (input) t roe_vpo t vmo_roe t vpo_roe t feopt t roe_vmo t period 1 2 3 4 5 6
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 67 figure 53. usb device timing diagram for data transfer from usb transceiver (rx) 4t vmo_roe ; usbd_vmo low to usbd_roe deactivated (includes se0) 248.90 249.13 248.90 249.13 ns 5t feopt ; se0 interval of eop 160.00 175.00 160.00 175.00 ns 6t period ; data transfer rate 11.97 12.03 11.97 12.03 mb/s table 27. usb device timing parameter table for data transfer from usb transceiver (rx) ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum 1t feopr ; receiver se0 interval of eop 82 ? 82 ? ns table 26. usb device timing parameter table for data transfer to usb transceiver (tx) ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum usbd_afe (output) usbd_roe (output) usbd_vpo (output) usbd_vmo (output) (output) usbd_suspnd (input) usbd_vp usbd_rcv (input) usbd_vm (input) t feopr 1
mc9328mxl advance information, rev. 5 68 freescale semiconductor specifications 3.17 i 2 c module the i 2 c communication protocol consists of seven elements: start, data source/recipient, data direction, slave acknowledge, da ta, data acknowledge, and stop. figure 54. definition of bus timing for i 2 c 3.18 synchronous serial interface the transmit and receive sections of the ssi can be synchronous or asynchrono us. in synchronous mode, the transmitter and the receiver use a common clock and frame synchronization signal. in asynchronous mode, the transmitter and receiver each have their own clock and frame synchronization signals. continuous or gated clock mode can be selected. in continuous mode, the clock runs continuously. in gated clock mode, the clock functions only during transmission. the internal and external clock timing diagrams are shown in figure 56 through figure 58 on page 70. normal or network mode can also be selected. in no rmal mode, the ssi functions with one data word of i/o per frame. in network mode, a frame can contain between 2 and 32 data words. network mode is typically used in star or ring-tim e division multiplex networ ks with other processors or codecs, allowing interface to time division multiplexed networks withou t additional logic. use of the gated clock is not allowed in network mode. these dist inctions result in the basic opera ting modes that allow the ssi to communicate with a wide variety of devices. table 28. i 2 c bus timing parameter table ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum 1 hold time (repeated) start condition 182 ? 160 ? ns 2 data hold time 01710150ns 3 data setup time 11.4 ? 10 ? ns 4 high period of the scl clock 80 ? 120 ? ns 5 low period of the scl clock 480 ? 320 ? ns 6 setup time for stop condition 182.4 ? 160 ? ns sda scl 1 2 3 4 6 5
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 69 note: srxd input in synchronous mode only. figure 55. ssi transmitter internal clock timing diagram figure 56. ssi receiver internal clock timing diagram stck output stfs (bl) output stfs (wl) output 1 2 6 8 10 11 stxd output srxd input 32 31 4 12 srck output srfs (bl) output srfs (wl) output 3 7 srxd input 13 14 1 5 9
mc9328mxl advance information, rev. 5 70 freescale semiconductor specifications figure 57. ssi transmitter external clock timing diagram figure 58. ssi receiver ex ternal clock timing diagram table 29. ssi (port c primary function) timing parameter table ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum internal clock operation 1 (port c primary function 2 ) 1 stck/srck clock period 1 95 ? 83.3 ? ns 2 stck high to stfs (bl) high 3 1.5 4.5 1.3 3.9 ns 3 srck high to srfs (bl) high 3 -1.2 -1.7 -1.1 -1.5 ns stck input 16 stfs (bl) input stfs (wl) input 17 18 22 24 26 stxd output srxd input 27 28 34 note: srxd input in synchronous mode only 33 20 15 srck input 16 srfs (bl) input srfs (wl) input 17 19 23 srxd input 29 30 21 25 15
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 71 4 stck high to stfs (bl) low 3 2.5 4.3 2.2 3.8 ns 5 srck high to srfs (bl) low 3 0.1 -0.8 0.1 -0.8 ns 6 stck high to stfs (wl) high 3 1.48 4.45 1.3 3.9 ns 7 srck high to srfs (wl) high 3 -1.1 -1.5 -1.1 -1.5 ns 8 stck high to stfs (wl) low 3 2.51 4.33 2.2 3.8 ns 9 srck high to srfs (wl) low 3 0.1 -0.8 0.1 -0.8 ns 10 stck high to stxd valid from high impedance 14.25 15.73 12.5 13.8 ns 11a stck high to stxd high 0.91 3.08 0.8 2.7 ns 11b stck high to stxd low 0.57 3.19 0.5 2.8 ns 12 stck high to stxd high impedance 12.88 13.57 11.3 11.9 ns 13 srxd setup time before srck low 21.1 ? 18.5 ? ns 14 srxd hold time after srck low 0 ? 0 ? ns external clock operation (port c primary function 2 ) 15 stck/srck clock period 1 92.8 ? 81.4 ? ns 16 stck/srck clock high period 27.1 ? 40.7 ? ns 17 stck/srck clock low period 61.1 ? 40.7 ? ns 18 stck high to stfs (bl) high 3 ? 92.8 0 81.4 ns 19 srck high to srfs (bl) high 3 ? 92.8 0 81.4 ns 20 stck high to stfs (bl) low 3 ? 92.8 0 81.4 ns 21 srck high to srfs (bl) low 3 ? 92.8 0 81.4 ns 22 stck high to stfs (wl) high 3 ? 92.8 0 81.4 ns 23 srck high to srfs (wl) high 3 ? 92.8 0 81.4 ns 24 stck high to stfs (wl) low 3 ? 92.8 0 81.4 ns 25 srck high to srfs (wl) low 3 ? 92.8 0 81.4 ns 26 stck high to stxd valid from high impedance 18.01 28.16 15.8 24.7 ns 27a stck high to stxd high 8.98 18.13 7.0 15.9 ns 27b stck high to stxd low 9.12 18.24 8.0 16.0 ns table 29. ssi (port c primary functi on) timing parameter table (continued) ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum
mc9328mxl advance information, rev. 5 72 freescale semiconductor specifications 28 stck high to stxd high impedance 18.47 28.5 16.2 25.0 ns 29 srxd setup time before srck low 1.14 ? 1.0 ? ns 30 srxd hole time after srck low 0 ? 0 ? ns synchronous internal clock operation (port c primary function 2 ) 31 srxd setup before stck falling 15.4 ? 13.5 ? ns 32 srxd hold after stck falling 0 ? 0 ? ns synchronous external clock operation (port c primary function 2 ) 33 srxd setup before stck falling 1.14 ? 1.0 ? ns 34 srxd hold after stck falling 0 ? 0 ? ns 1. all the timings for the ssi are given for a non-inve rted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame sync (tfsi/rfsi = 0). if the pol arity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal stck/srck and/or the frame sync stfs/srfs shown in the tables and in the figures. 2. there are 2 sets of i/o signals for the ssi module. they are from port c prim ary function (pad 257 to pad 261) and port b alternate function (pad 283 to pad 288 ). when ssi signals are configured as outputs, they can be viewed both at port c primary function and port b alternate function. when ssi signals are configured as input, the ssi module selects the inpu t based on status of the fm cr register bits in the clock controller module (crm). by default, the input are selected from port c primary function. 3. bl = bit length; wl = word length. table 30. ssi (port b alternat e function) timing parameter table ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum internal clock operation 1 (port b altern ate function 2 ) 1 stck/srck clock period 1 95 ? 83.3 ? ns 2 stck high to stfs (bl) high 3 1.7 4.8 1.5 4.2 ns 3 srck high to srfs (bl) high 3 -0.1 1.0 -0.1 1.0 ns 4 stck high to stfs (bl) low 3 3.08 5.24 2.7 4.6 ns 5 srck high to srfs (bl) low 3 1.25 2.28 1.1 2.0 ns 6 stck high to stfs (wl) high 3 1.71 4.79 1.5 4.2 ns 7 srck high to srfs (wl) high 3 -0.1 1.0 -0.1 1.0 ns 8 stck high to stfs (wl) low 3 3.08 5.24 2.7 4.6 ns table 29. ssi (port c primary functi on) timing parameter table (continued) ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 73 9 srck high to srfs (wl) low 3 1.25 2.28 1.1 2.0 ns 10 stck high to stxd valid from high impedance 14.93 16.19 13.1 14.2 ns 11a stck high to stxd high 1.25 3.42 1.1 3.0 ns 11b stck high to stxd low 2.51 3.99 2.2 3.5 ns 12 stck high to stxd high impedance 12.43 14.59 10.9 12.8 ns 13 srxd setup time before srck low 20 ? 17.5 ? ns 14 srxd hold time after srck low 0 ? 0 ? ns external clock operation (port b alternate function 2 ) 15 stck/srck clock period 1 92.8 ? 81.4 ? ns 16 stck/srck clock high period 27.1 ? 40.7 ? ns 17 stck/srck clock low period 61.1 ? 40.7 ? ns 18 stck high to stfs (bl) high 3 ? 92.8 0 81.4 ns 19 srck high to srfs (bl) high 3 ? 92.8 0 81.4 ns 20 stck high to stfs (bl) low 3 ? 92.8 0 81.4 ns 21 srck high to srfs (bl) low 3 ? 92.8 0 81.4 ns 22 stck high to stfs (wl) high 3 ? 92.8 0 81.4 ns 23 srck high to srfs (wl) high 3 ? 92.8 0 81.4 ns 24 stck high to stfs (wl) low 3 ? 92.8 0 81.4 ns 25 srck high to srfs (wl) low 3 ? 92.8 0 81.4 ns 26 stck high to stxd valid from high impedance 18.9 29.07 16.6 25.5 ns 27a stck high to stxd high 9.23 20.75 8.1 18.2 ns 27b stck high to stxd low 10.60 21.32 9.3 18.7 ns 28 stck high to stxd high impedance 17.90 29.75 15.7 26.1 ns 29 srxd setup time before srck low 1.14 ? 1.0 ? ns 30 srxd hold time after srck low 0 ? 0 ? ns table 30. ssi (port b alternate funct ion) timing parameter table (continued) ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum
mc9328mxl advance information, rev. 5 74 freescale semiconductor specifications synchronous internal clock operation (port b alternate function 2 ) 31 srxd setup before stck falling 18.81 ? 16.5 ? ns 32 srxd hold after stck falling 0 ? 0 ? ns synchronous external clock operation (port b alternate function 2 ) 33 srxd setup before stck falling 1.14 ? 1.0 ? ns 34 srxd hold after stck falling 0 ? 0 ? ns 1. all the timings for the ssi are given for a non-inve rted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame sync (tfsi/rfsi = 0). if the po larity of the clock and/or the frame sync have been inverted, all the timing remains valid by invertin g the clock signal stck/srck and/or the frame sync stfs/srfs shown in the tables and in the figures. 2. there are 2 set of i/o signals for the ssi module. th ey are from port c primar y function (pad 257 to pad 261) and port b alternate function (pad 283 to pad 288). when ssi signals are configured as outputs, they can be viewed both at port c primary function and port b alternate function. when ssi signals are configured as inputs, the ssi module selects the input based on fmcr r egister bits in the clock controller module (crm). by default, the input are selected from port c primary function. 3. bl = bit length; wl = word length. table 30. ssi (port b alternate funct ion) timing parameter table (continued) ref no. parameter 1.8v 0.10v 3.0v 0.30v unit minimum maximum minimum maximum
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 75 3.19 cmos sensor interface the cmos sensor interface (csi) module consists of a control register to configure the interface timing, a control register for statistic data generation, a status register, interface logic, a 32 32 image data receive fifo, and a 16 32 statistic data fifo. 3.19.1 gated clock mode figure 59 shows the timing diagram when the cmos sensor output data is configured for negative edge and the csi is programmed to received data on the positive edge. figure 60 on page 76 shows the timing diagram when the cmos sensor output data is configured for positive edge and the csi is prog rammed to received data in negative edge. the parameters for the timing di agrams are listed in table 31 on page 76. figure 59. sensor output data on pixel clock falling edge csi latches data on pixel clock rising edge vsync hsync pixclk data[7:0] valid data valid data 2 1 7 5 6 3 4 valid data
mc9328mxl advance information, rev. 5 76 freescale semiconductor specifications figure 60. sensor output data on pixel clock rising edge csi latches data on pixel clock falling edge the limitation on pixel clock rise time / fa ll time are not specified. it should be calculated from the hold time and setup time, according to: rising-edge latch data max rise time allowed = (positiv e duty cycle - hold time) max fall time allowed = (nega tive duty cycle - setup time) in most of case, duty cycle is 50 / 50, therefore max rise time = (period / 2 - hold time) max fall time = (period / 2 - setup time) for example: given pixel clock period = 10ns, duty cycle = 50 / 50, hold tim e = 1ns, setup time = 1ns. positive duty cycle = 10 / 2 = 5ns => max rise time allowed = 5 - 1 = 4ns table 31. gated clock mode timing parameters ref no. parameter min max unit 1 csi_vsync to csi_hsync 180 ? ns 2 csi_hsync to csi_pixclk 1 ? ns 3 csi_d setup time 1 ? ns 4 csi_d hold time 1 ? ns 5 csi_pixclk high time 10.42 ? ns 6 csi_pixclk low time 10.42 ? ns 7 csi_pixclk frequency 0 48 mhz vsync hsync pixclk data[7:0] valid data valid data valid data 1 2 3 4 5 6 7
specifications mc9328mxl advance information, rev. 5 freescale semiconductor 77 negative duty cycle = 10 / 2 = 5ns => max fall time allowed = 5 - 1 = 4ns falling-edge latch data max fall time allowed = (nega tive duty cycle - hold time) max rise time allowed = (pos itive duty cycle - setup time) 3.19.2 non-gated clock mode figure 61 shows the timing diagram when the cmos sensor output data is configured for negative edge and the csi is programmed to received data on the positive edge. figure 62 on page 78 shows the timing diagram when the cmos sensor output data is configured for positive edge and the csi is prog rammed to received data in negative edge. the parameters for the timing di agrams are listed in table 32 on page 78. figure 61. sensor output data on pixel clock falling edge csi latches data on pixel clock rising edge vsync pixclk data[7:0] valid data valid data valid data 1 2 3 4 5 6
mc9328mxl advance information, rev. 5 78 freescale semiconductor specifications figure 62. sensor output data on pixel clock rising edge csi latches data on pixel clock falling edge the limitation on pixel clock rise time / fa ll time are not specified. it should be calculated from the hold time and setup time, according to: max rise time allowed = (positiv e duty cycle - hold time) max fall time allowed = (nega tive duty cycle - setup time) in most of case, duty cycle is 50 / 50, therefore: max rise time = (period / 2 - hold time) max fall time = (period / 2 - setup time) for example: given pixel clock period = 10ns, duty cycle = 50 / 50, hold tim e = 1ns, setup time = 1ns. positive duty cycle = 10 / 2 = 5ns => max rise time allowed = 5 - 1 = 4ns negative duty cycle = 10 / 2 = 5ns => max fall time allowed = 5 - 1 = 4ns falling-edge latch data max fall time allowed = (nega tive duty cycle - hold time) max rise time allowed = (pos itive duty cycle - setup time) table 32. non-gated clock mode parameters ref no. parameter min max unit 1 csi_vsync to csi_pixclk 180 ? ns 2 csi_d setup time 1 ? ns 3 csi_d hold time 1 ? ns 4 csi_pixclk high time 10.42 ? ns 5 csi_pixclk low time 10.42 ? ns 6 csi_pixclk frequency 0 48 mhz vsync pixclk data[7:0] valid data valid data valid data 1 2 3 4 5 6
mc9328mxl advance information, rev. 5 freescale semiconductor 79 pin-out and package information 4 pin-out and package information table 33 illustrates the package pin a ssignments for the 256-pin mapbga package. table 33. mc9328mxl 256 mapbga pin assignments 1234 5678910111213141516 a nvss1 dat3 clk nvss4 usbd_ afe nvdd4 nvss3 uart1_ rts uart1_ rxd nvdd3 n.c. n.c. qvdd4 n.c. n.c. n.c. b a24 dat1 cmd ssi1_rxdat usbd_ roe usbd_vp ssi0_ rxclk ssi0_ txclk spi1_ sclk n.c. n.c. n.c. qvss4 n.c. n.c. n.c. c a23 d31 dat0 ssi1_rxclk usbd_ rcv uart2_ cts uart2_ rxd ssi0_ rxfs uart1_ txd n.c. n.c. n.c. n.c. n.c. n.c. n.c. d a22 d30 d29 ssi1_rxfs usbd_ suspnd usbd_ vpo usbd_ vmo ssi0_ rxdat spi1_ spi_rdy n.c. n.c. n.c. n.c. n.c. n.c. n.c. e a20 a21 d28 d26 dat2 usbd_vm uart2_ rts ssi0_ txdat spi1_ss n.c. n.c. n.c. n.c. n.c. n.c. n.c. f a18 d27 d25 a19 a16 ssi1_ txfs uart2_ txd ssi0_ txfs spi1_ miso n.c. n.c. rev n.c. n.c. lsclk spl_spr g a15 a17 d24 d23 d21 ssi1_ txdat ssi1_ txclk uart1_ cts spi1_ mosi n.c. cls contrast oe_acd hsync vsync ld1 h a13 d22 a14 d20 nvdd1 nvdd1 nvss1 qvss1 qvdd1 ps ld0 ld2 ld4 ld5 ld9 ld3 j a12 a11 d18 d19 nvdd1 nvdd1 nvss1 nvdd1 nv ss2 nvss2 ld6 ld7 ld8 ld11 qvdd3 qvss3 k a10 d16 a9 d17 nvdd1 nvss1 nvss1 nvdd1 nvdd2 nvdd2 ld10 ld12 ld13 ld14 tout2 ld15 l a8 a7 d13 d15 d14 nvdd1 nvss1 cas tck tin pwmo csi_mclk csi_d0 csi_d1 csi_d2 csi_d3 m a5 d12 d11 a6 sdclk nvss1 rw ma10 ras reset_in big_endi an csi_d4 csi_ hsync csi_vsync csi_d6 csi_d5 n a4 eb1 d10d7 a0 d4pa17d1dqm1reset_sf reset_ out boot2 csi_ pixclk csi_d7 tms tdi p a3 d9 eb0 cs3 d6 ecb d2 d3 dqm3 sdcke1 boot3 boot0 trst i2c_clk i2c_data xtal32k r eb2 eb3 a1 cs4 d8 d5 lba bclk 1 1. burst clock d0 dqm0 sdcke0 por boot1 tdo qvdd2 extal32k t nvss1 a2 oe cs5 cs2 cs1 cs0 ma11 dqm2 sdwe clko avdd1 tristate extal16m xtal16m qvss2
mc9328mxl advance information, rev. 5 80 freescale semiconductor pin-out and package information table 34 illustrates the package pin a ssignments for the 225-pin pbga package. table 34. mc9328mxl 225 pbga pin assignments 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 a cmd ssi1_ rxclk ssi1_ txclk usbd_ roe usbd_ suspnd usbd_vm ssi0_ rxfs ssi0_ txclk spi1_rdy spi1_ sclk rev ps ld2 ld4 ld5 b dat3 clk ssi1_ rxdat usbd_ afe usbd_rcv usbd_ vmo ssi0_ rxdat uart1_ txd spi1_ss lsclk spl_ spr ld0 ld3 ld6 ld7 c d31 dat0 ssi1_ rxfs ssi1_ txfs dat2 usbd_ vpo uart2_ rxd ssi0_ txfs uart1_ rts contrast vsync ld8 ld9 ld12 nvdd2 d a23 a24 dat1 ssi1_ txdat nvdd1 usbd_vp qvdd4 uart2_ txd nvdd3 spi1_ mosi hsync ld1 ld11 tout2 ld13 e a21 a22 d30 d29 nvdd1 qvss uart2_ rts uart1_ rxd uart1_ cts spi1_ miso oe_ acd ld10 tin csi_d0 csi_ mclk f a20 a19 d28 d27 nvdd1 nvdd1 uart2_ cts ssi0_ rxclk ssi0_ txdat cls qvdd3 ld14 ld15 csi_d2 csi_d4 g a17 a18 d26 d25 nvdd1 nvss nvdd4 nvss nvss qvss pwmo csi_d3 csi_d7 csi_hsync csi_d5 h a15 a16 d23 d24 d22 nvss nvss nvss nvss nvdd2 csi_d1 csi_ vsync csi_ pixclk i2c_data tms j a14 a12 d21 d20 nvdd1 nvss nvss qvdd1 nvss csi_d6 i2c_ clk tck tdo boot1 boot0 k a13 a11 cs2 d19 nvdd1 nvss qvss nvdd1 nvss d1 boot2 tdi big_ endian reset_ out xtal32k l a10 a9 d17 d18 nvdd1 nvdd1 cs5 d2 ecb nvss nvss por qvss xtal16m extal32k m d16 d15 d13 d10 eb3 nvdd1 cs4 cs1 bclk 1 1. burst clock rw nvss boot3 qvdd2 reset_in extal16m n a8 a7 d12 eb0 d9 d8 cs3 cs0 pa17 d0 dqm2 dqm0 sdcke0 tristate trst p d14 a5 a4 a3 a2 a1 d6 d5 ma10 ma11 dqm1 ras sdcke1 clko resetsf r a6 d11 eb1 eb2 oe d7 a0 sdclk d4 lba d3 dqm3 cas sdwe avdd1
pin-out and package information mc9328mxl advance information, rev. 5 freescale semiconductor 81 4.1 mapbga 256 package dimensions figure 63 illustrates the 256 mapbga 14 mm 14 mm 1. 30 mm package, which has 0.8 mm spacing between the pads. the device designator for the mapbga package is vh. figure 63. mc9328mxl 256 mapbga mechanical drawing notes: 1. all dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14 5m-1994. 3. maximum solder ball diameter measured parallel to datum a. 4. datum a, the seating plane is defined by spherical crowns of the solder balls. case outline 1367 side view bottom view top view
mc9328mxl advance information, rev. 5 82 freescale semiconductor pin-out and package information 4.2 pbga 225 package dimensions figure 64 illustrates the 225 pb ga 13 mm 13 mm 0.8 mm package. figure 64. mc9328mxl 225 pbga mechanical drawing top view bottom view side view case outline 1304b notes: 1. all dimensions are in millimeters. 2. dimensions and tolerances per asme y14 5m-1994. 3. maximum solder ball diameter measured parallel to datum a. 4. datum a, the seating plane is defined by spherical crowns of the solder balls. 5. parallelism measurement shall exclude an y effect of mark on top surface of package.
mc9328mxl advance information, rev. 5 freescale semiconductor 83 notes
mc9328mxl/d rev. 5 08/2004 how to reach us: usa/europe/locations not listed: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-521-6274 or 480-768-2130 japan: freescale semiconductor japan ltd. technical information center 3-20-1, minami-azabu, minato-ku tokyo 106-8573, japan 81-3-3440-3569 asia/pacific: freescale semiconductor hong kong ltd. 2 dai king street tai po industrial estate tai po, n.t., hong kong 852-26668334 home page: www.freescale.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circui ts or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does freescale semiconductor assume any liability arising out of the application or use of any product or ci rcuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor dat a sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. learn more : for more information about freescale products, please visit www.freescale.com. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of thei r respective owners. the arm powered logo is the registered trademark of arm limited. arm9, arm920t, and arm9tdmi are the trademarks of arm limited. ? freescale semiconductor, inc. 2004. all rights reserved.

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